This invention relates to memory elements, and more particularly, to circuitry for ensuring that memory elements exhibit satisfactory immunity to soft error upset events.
Integrated circuits often contain volatile memory elements such as static random-access memory (SRAM) elements. Memory elements can be used to temporarily store data during data processing operations. For example, an integrated circuit that contains processing logic may contain an array of SRAM elements for storing data that is used by the processing logic. Memory elements may also be used in memory chips. Circuits such as field-programmable gate arrays and other programmable devices may contain memory elements that store configuration data for configuring programmable logic.
A volatile memory element retains data only so long as an integrated circuit is powered. In the event of power loss, the data in the volatile memory element is lost. Although nonvolatile memory elements such as memory elements based on electrically-erasable programmable read-only memory technology are not subject to data loss in this way, it is often not desirable or possible to fabricate nonvolatile memory elements as part of a given integrated circuit.
Volatile memory elements are subject to a phenomenon known as soft error upset. Soft error upset events are caused by cosmic rays and radioactive impurities embedded in integrated circuits and their packages. Cosmic rays and radioactive impurities generate high-energy atomic particles such as neutrons and alpha particles. The memory elements typically contain transistors that are formed from silicon. When an atomic particle strikes the silicon in a memory element, electron-hole pairs are generated. The electron-hole pairs create a conduction path that can cause a charged node in the memory element to discharge and the state of the memory element to flip. If, for example, a “1” was stored in the memory element, a soft error upset event could cause the “1” to change to a “0.”
Upset events in an integrated circuit corrupt the data stored in the memory elements and can have serious repercussions for system performance. In certain system applications such as remote installations of telecommunications equipment, it is extremely burdensome to repair faulty equipment. Unless programmable logic devices and other integrated circuits demonstrate good immunity to soft error upset events, they will be unsuitable for these types of applications.
One way to provide integrated circuits with tolerance to soft error upset events involves periodically checking the status of the bits in a memory array. Using error correction codes such as cyclic redundancy check codes, redundant information may be stored in a section of a memory array. Error checking circuitry can periodically read out the data in a memory array and the corresponding error correction codes to determine whether errors are present in the data. If an error is detected, appropriate action can be taken. For example, in some devices it may be possible to reload a copy of the correct data into the memory array.
The process of periodically reading out the data from a memory array can, however, consume undesired power on an integrated circuit. The circuitry that is used to support these periodic data checks must also be incorporated into the integrated circuit, which can increase circuit cost and complexity. Moreover, there is the possibility that the act of reading out the contents of a memory element will disturb the state of the element, even with properly designed read circuits.
It would therefore be desirable to be able to provide memory circuitry with improved tolerance to soft error upset events.